1. Field of the Invention
This invention relates to integrated processing systems and more particularly to a high performance integrated processor architecture that supports an external derivation of a low performance peripheral bus from a multiplexed peripheral bus.
2. Description of the Relevant Art
FIG. 1 is a block diagram of a computer system 10 including a microprocessor (CPU) 12, a CPU local bus 14 coupled to microprocessor 12, and a memory controller 16 and a local bus peripheral device 18 coupled to CPU local bus 14. A system memory 18 is further shown coupled to memory controller 16. A PCI standard bus 20 is coupled to CPU local bus 14 through a PCI bus bridge 22, and an ISA (Industry Standard Architecture) bus 24 is coupled to CPU local bus 14 through ISA bus bridge 26. A PCI peripheral device 28 is finally shown coupled to PCI bus 20, and an ISA peripheral device 30 is shown coupled to ISA bus 24.
Microprocessor 12 is illustrative of, for example, a model 80486 microprocessor, and CPU local bus 14 is exemplary of an 80486-style local bus. The CPU local bus 14 includes a set of data lines D[31:0], a set of address lines A[31:0], and a set of control lines (not shown individually). Details regarding the various bus cycles and protocols of the 80486 CPU local bus 14 are described in a host of publications of the known prior art.
PCI bus bridge 22 provides a standard interface between the CPU local bus 14 and the PCI bus 20. As such, PCI bus bridge 22 orchestrates the transfer of data, address, and control signals between the two buses. PCI bus 20 is high performance peripheral bus that supports burst-mode data transfers and that includes multiplexed data/address lines. PCI peripheral device 28 is illustrative of, for example, any PCI compatible peripheral device such as a disk controller.
The ISA bus 24 of FIG. 1 supports the connection of ISA peripheral devices within computer system 10. ISA bus 26 orchestrates the transfer of data, address, and control signals between CPU local bus 14 and ISA bus 24. Although ISA bus 24 is a relatively low performance bus, the inclusion of ISA bus 24 and ISA bus bridge 26 within computer system 10 advantageously allows ISA peripheral devices to be connected within the system. It is noted that this feature is advantageous since a wide variety of ISA compatible peripheral devices are currently available.
Microprocessor 12, memory controller 16, PCI bus bridge 22, and ISA bus bridge 26 have traditionally been fabricated on separate integrated circuit chips. A new trend in computing systems has developed, however, that involves the incorporation of a CPU core along with a variety of peripherals on a single integrated processor chip. An exemplary integrated processor chip includes a bus bridge that provides a high performance interface between an internal CPU local bus and, for example, an external PCI bus. By providing a high performance interface to an external PCI bus, relatively high performance characteristics can be achieved with respect to external data transfers. However, since an ISA bus interface is typically not incorporated on such an integrated processor chip, ISA compatible peripheral devices are not supported by the system. Although the ISA peripheral devices are typically relatively low performance devices, a wide variety of ISA peripherals are available, and the cost of such peripherals is relatively low. Thus, for certain applications, an integrated processor incorporating only a PCI bus bridge is unsuitable. Although it is evident that an ISA bus bridge could be incorporated on the integrated processor to provide an interface to an external ISA bus, an additional set of dedicated package pins would be required for the ISA bus. This would result in a high overall cost of the integrated processor since a relatively large number of external pins would be required on the integrated circuit package and since the required die size of the integrated processor would be relatively large due to the additional bond wire pads.